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JBlec2's avatar
JBlec2
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Nios II Code comparing with Hardware Code

Hi , i have a little Algorithm written for my NIOS II . And it works . I recently tested it. Now i want to implement this algorithm on my FPGA with system Verilog and also compare the speed. So first...
MEIYAN_L_Intel's avatar
MEIYAN_L_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi,

Can you try to use Intel High Level Synthesis Compiler to compile the C programming code and generate the Verilog file.

The document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-getting-started.pdf shows the tutorial for compile the example C code and generate the Verilog file.

For more information about Intel HLS, you can look at the document as below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/mnl-hls-reference.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-best-practices.pdf

Thanks.