Nios II Building Error

From a quick look it seems that your problem comes from the fact that you defined some of the I/O in the "clk" domain when those signals are generated from a different clock in the system, that has a different frequency. You should define all your I/O delays for the flash and SRAM I/O relative to the ssram_clk clock.

I fixed all the failing paths, but Nios II failed to verify sram. :D

Now you should run a memory test.

The memory test software also failed to verify sram. This is the first time I constraint the sram, but I think I do it correctly. I can send the project if you want to have a look. :D

Without the hardware it will be difficult to debug the project... Which test is failing exactly? Do you have any error message?

Hello World Small and Memory Test Small both gave this error:

Using cable "USB-Blaster ", device 1, instance 0x00
Pausing target processor: OK
Initializing CPU cache (if present)
OK
Downloaded 8KB in 0.1s
Verifying 01200020 ( 0%)
Verify failed between address 0x1200020 and 0x1201DAF
Leaving target processor paused

To do a memory test of SRAM you really want to load the test program to internal memory.

Can you tell me specificly how to load program to internal memory? :)

First you need an onchip memory in your system, connected to both the Nios CPU's instruction and data masters. Then in the BSP settings, set all the memory configurations to your on-chip memory. If the memory is small, select the small C option, and enable the compiler optimisations.

Thank you for your guide. I successfully loaded the software to FPGA, and I got flash memory test failed:

 -Data bus test failed at bit 0x1

 -Data bus test passed
 -Address bus test passed
 -Byte and half-word access test passed
 -Testing each bit in memory device.