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Altera_Forum
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13 years ago

Nios II Building Error

I got this error when building a Nios II project. Please help me fix it. :) 


alt_sys_init.c:(.text+0x8): warning: Error: Interrupt not connected for JTAG_UART. You have selected the interrupt driven version of the ALTERA Avalon JTAG UART driver, but the interrupt is not connected for this device. You can select a polled mode driver by checking the 'small driver' option in the HAL configuration window, or by using the -DALTERA_AVALON_JTAG_UART_SMALL preprocessor flag.
alt_sys_init.c:(.text+0x8): undefined reference to `__alt_invalid'
collect2: ld returned 1 exit status
make: ***  Error 1

21 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    As the error message suggests, either configure the BSP to use the small drivers so that you don't use interrupts, or go back to SOPC Builder / QSys and connect the JTAG Uart's interrupt port to the Nios CPU.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks Daixiwen. Now I get this error: :rolleyes: 

    Connected system timestamp not found on target at expected base address.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    It looks like the FPGA configuration you have doesn't correspond to the SOPC definition that the BSP used to compile the software. Be sure that you have the right configuration.

    You can follow those steps each time you modify the SOPC project:[list][*]save SOPC project and generate it[*]compile the hardware project in Quartus[*]open the Nios IDE, check that it's pointing to the right .sopcinfo file[*]compile the software project[*]upload the correct .sof file to the FPGA (careful! if you are using IP cores without their license, the file could be a *_time_limited.sof instead of the regular one)[*]upload the software[/list]
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I just got this warning in Quartus: 

    Critical Warning: Timing requirements not met

    and error in Nios II: 

    Verify failed between address 0x1100020 and 0x1100177

    :confused:
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    For the riming warning you need to open Timequest and find out the top failing paths to determine what to do.

    For the second error, first check that your main memory is indeed at address 0x1100000, and then try to run a memory test on it. But you should fix the timing problem first.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I checked the sram in qsys, it was indeed at address 0x01000000 to 0x011fffff.

    In TimeQuest, I found this, but I didn't know what to do:

    Clock ______________ Slack __________ End Point TNS

    clk_________________-1.224___________-1.596

    pll|sd1|pll7|clk[0] ____ 2.057___________0.000

    ssram_clk____________4.926___________0.000

    tck_________________18.366__________0.000

    altera_reserved_tck___45.114__________0.000

    :D
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    There is another report in Timequest that is called "Top Failing Paths". Is will probably be somewhere in the setup summary. Just look up for categories that are in red.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I find it strange that you have two different clocks on those paths... Could you describe your clock distribution, and share your sdc constraints files?