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Altera_Forum
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12 years ago

NIOS II 32 bit data master -> Avalon MM PCIe 64 bit TX slave

I had a system working where the DMA controller ( 64 bit ) was reading and writing to the TX port of the PCIe TX port .

I now have a situation where I want the NIOS II data master ( 32 bit ) to read and write the TX port of the PCIe IP to get to system memory via the PCIe link.

Writes seem to go nowhere and reads hand.

I believe the fabric should take care of the 32 -64 bit data width mismatch but not sure.

Also not sure exactly how to make the NIOS II read or write .. I have an int pointer that I am making *ptr references via where ptr = the QSYS address of the TX port.

The TX port has 2 mappings or 4k byte blocks .

I could try getting the NIOS to set up the DMA transfer to see if that works better but really want the NIOS II to make references to system memory via the PCIe link.

Also , the QSYS says that address bit 31 must be '0' ... for NIOS ,... is there a reasone for that ?

Thanks in advance, Bob.

13 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Hi Bob,

    Thanks for your reply.

    I will check this and revert you back.

    Thanks & Regards,

    Varun
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Bob,

    I started to create the design, that access the x86(Atom) processor DDR3 memory from Nios II through PCIe interface using "txs" signal. But I required some help from your side.

    - I went through user guide for PCIe IP core of Altera and the internal operation of "txs" signal are not very clearly documented. So, can you refer me any specific document on how PCIe IP "txs" signal works.

    - What should be the physical address that would be assigned to "txs slave port" in PCIe hard IP?

    - As of my understanding, the hardware(Qsys) side connection is only from Nios II to PCIe Hard IP "txs" signal. All other access should be done on software side that is:

    - how x86(Atom) processor DDR3 memory is accessed in software?

    It is possible to share software reference to access x86(Atom) processor memory using "txs" signal of PCIe hard IP.

    Thanks & Regards,

    Varun
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Bod,

    I have created the hardware design with Nios II connected to x86 via PCIe hard ip to access the x86 memory.

    I like to know how to access txs signal in software?

    Can you please share me if you have any software file for Nios II SDK.

    Thanks & Regards,

    Varun