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Altera_Forum
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12 years ago

NIOS II 32 bit data master -> Avalon MM PCIe 64 bit TX slave

I had a system working where the DMA controller ( 64 bit ) was reading and writing to the TX port of the PCIe TX port . I now have a situation where I want the NIOS II data master ( 32 bit ) to r...
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Altera_Forum
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10 years ago

Hi Bob,

I started to create the design, that access the x86(Atom) processor DDR3 memory from Nios II through PCIe interface using "txs" signal. But I required some help from your side.

- I went through user guide for PCIe IP core of Altera and the internal operation of "txs" signal are not very clearly documented. So, can you refer me any specific document on how PCIe IP "txs" signal works.

- What should be the physical address that would be assigned to "txs slave port" in PCIe hard IP?

- As of my understanding, the hardware(Qsys) side connection is only from Nios II to PCIe Hard IP "txs" signal. All other access should be done on software side that is:

- how x86(Atom) processor DDR3 memory is accessed in software?

It is possible to share software reference to access x86(Atom) processor memory using "txs" signal of PCIe hard IP.

Thanks & Regards,

Varun