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Altera_Forum
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21 years agoNios I - Wrong IRQ Vector
I recently noticed a problem with a Nios (not Nios II) design implemented on an APEX EP20K device. At initialization, I set all entries in the interrupt vector table to point to the same routine: it ...
Altera_Forum
Honored Contributor
21 years ago<div class='quotetop'>QUOTE </div>
--- Quote Start --- Is it still necessary to synchronize them with the Nios clock before bringing them to the PIO?[/b] --- Quote End --- Yes, because the signal connected to the IRQ pin on your PIO must not change within the specified setup and hold times for the interrupt controller. As the frequency of interrupts increases, so does the probability of an asynchronous input violating these setup and hold times. A single d-type flip-flop per input should cure the problem (two, to be really sure). <div class='quotetop'>QUOTE </div> --- Quote Start --- The other interrupt is from a standard Nios timer (so I would assume it is inherently synchronized).[/b] --- Quote End --- Yes, that's correct.