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Altera_Forum's avatar
Altera_Forum
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20 years ago

nios debug freezing

Normally,my design works well, but sometimes I do a little change in the fpga design,such as put a signal on an output pin for test. run nios ide. after nios finish downloud SW and jump in debug wi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

It's not unheard of that small design changes affect borderline timing on some other component (memory, I/O) to the point where the program crashes or the debugger can't communicate any more.

First thing to check might be the timing on RAM, if you have that.