Nios data bus interface less than 32-bits

It's not really a trick but make sure you include byte enables on your DPRAM slave interfaces. This will make sure when the CPU performs say a 32-bit read to the 16-bit slave port two back to back 16-bit reads will be return instead of a single 16-bit read with the upper 16-bit padded to zeros. Since you are using on-chip memories you can set the read latency to be fixed when defining the slave port in component editor. If you don't register the outputs of the memory the latency will be 1, otherwise it'll be two. SOPC Builder will generate all the necessary logic to make sure the reads are returned to the master correctly without the need of a wait request signal. Now if your component is more than just a DPRAM behind the slave port then you may need to create a variable latency slave instead (see Avalon spec to find out what is needed in that case)