Nios data bus interface less than 32-bits

The nios cpu itself always issues 32bit reads (all bytes selected) and 32bit writes (required byte selects), so something external (to the cpu) has to do the bus width conversion.

I believe Altera supplies a 'pipelined' bus width adapter which will do the job. But I've no idea what the actual performance cost is for cpu memeory accesses (and cache line transfers).

I know the nios cpu stalls until avalon read/write cycles complete, so 'posting' writes within the external slave may help. I think the Altera sdram block posts and merges writes.

The PDRAM interface might be such that it is more appropriate to do the convertion youself