Honored ContributorHello,
I have successfully interfaced a DPRAM with a 32-bit data bus to the Nios processor in an Arria II GX FPGA using SOPC builder. Now I need to interface multiple other DPRAMs which have less the 32-bit data busses to the Nios. Are there any special techniques/tricks which you need to use to accomodate a less than 32-bit data bus interface to the Nios? Thanks.
Honored ContributorThe nios cpu itself always issues 32bit reads (all bytes selected) and 32bit writes (required byte selects), so something external (to the cpu) has to do the bus width conversion.
I believe Altera supplies a 'pipelined' bus width adapter which will do the job. But I've no idea what the actual performance cost is for cpu memeory accesses (and cache line transfers). I know the nios cpu stalls until avalon read/write cycles complete, so 'posting' writes within the external slave may help. I think the Altera sdram block posts and merges writes. The PDRAM interface might be such that it is more appropriate to do the convertion youselfHonored ContributorYou may also use mixed width fifo.
Honored ContributorIt's not really a trick but make sure you include byte enables on your DPRAM slave interfaces. This will make sure when the CPU performs say a 32-bit read to the 16-bit slave port two back to back 16-bit reads will be return instead of a single 16-bit read with the upper 16-bit padded to zeros. Since you are using on-chip memories you can set the read latency to be fixed when defining the slave port in component editor. If you don't register the outputs of the memory the latency will be 1, otherwise it'll be two. SOPC Builder will generate all the necessary logic to make sure the reads are returned to the master correctly without the need of a wait request signal. Now if your component is more than just a DPRAM behind the slave port then you may need to create a variable latency slave instead (see Avalon spec to find out what is needed in that case)
