ZhiqiangLiang
Occasional Contributor
Occasional ContributorNIOS connected to IRQ from FPGA but not PIO
Hi,
I firstly created a new IP, and I add the interrupt sender FPGA_INTS. please see my picture below.
I then connect the FPGA_INTS to irq of NIOS. Please see my picture below.
The generated system.h file is shown in the following picture.
The questions:
1) I notice that a few xxxx_IRQ_INTERRUPT_CONTROLLER_ID are -1, and a few YYY_IRQ_INTERRUPT_CONTROLLER_ID are 0. No other value of XXX_IRQ_INTERRUPT_CONTROLLER_ID. is this correct?
2) the FPGA_INTS is assigned in my verilog code in the IP, and it is 32bit width which is 32 interrupt. how to write C code to accept each interrupt?
3) the FPGA_INTS is a 32bit-register in Verilog. The lowest 4bits of FPGA_INTS is useful, however Platform Designer reports error when I connect the 4bits FPGA_INTS interrupt to irq of NIOS II. so I extend the FPGA_INTS to 32bits in Verilog code and mask [28:4] bit of FPGA_INTS. is what I did correct?
unsigned int HD_irq_context;
void HD_interrupt_handler(void * HD_irq_context)
{
log("in HD interrupt == 0x%x\n", *((unsigned int*)HD_irq_context));
printf("==============================\n");
return;
}
void HD_interrupt_setup( void )
{
void * pISR_contex = ( void *) &HD_irq_context;
alt_ic_isr_register(
BF5V_0_IRQ_INTERRUPT_CONTROLLER_ID,
BF5V_0_IRQ,
HD_interrupt_handler,
pISR_contex,
0x0);
}
void HD_interrupt_handler(void * HD_irq_context)
{
log("in HD interrupt == 0x%x\n", *((unsigned int*)HD_irq_context));
printf("==============================\n");
return;
}
void HD_interrupt_setup( void )
{
void * pISR_contex = ( void *) &HD_irq_context;
alt_ic_isr_register(
BF5V_0_IRQ_INTERRUPT_CONTROLLER_ID,
BF5V_0_IRQ,
HD_interrupt_handler,
pISR_contex,
0x0);
}
