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Honored Contributor
Honored ContributorNios 2 processor cores
We've just had our Nios 2 DKs installed. Since we are targeting a standard core to use in a Cyclone device, the software engineer asked if there were a way to not use the instruction bus cache a...
Altera_ForumHonored Contributor
Honored ContributorI refactored the perl code used to generate the Nios II cores to allow more sharing
and more options. That will show up in Nios II 1.1 near the end of the year. I'm not sure which of these will make it into that release because adding options dramatically increases our testing burden. Here's some possible options: - Static or dynamic branch prediction (Nios II/s currenly uses static, Nios II/f currently uses dynamic) - Optional instruction cache for Nios II/s and Nios II/f - Optional data cache for Nios II/f - Hardware divide support for Nios II/s (your specific request) Besides divide for Nios II/s, do any of these look interesting to you?
