Nios 2 IDE download verification error

Slacker,

I agree completely. But as you see in the symbol table above, all user code is placed from address 0x00200000 which is the base of my external SRAM. The only code at address 0 is automatically added, due to the fact, reset vector is assigned to epcs_controller. And epcs_controller suddenly got an offset of 0x20 so the linker doesn't see any conflict. I think Altera uses an overlay scheme not considered by the debugging load / verify process.

It would be interesting what address is used for __reset in freecks design, where the error occurs at address 0x00800020.

Mike