Honored Contributor
Honored ContributorYou will find the Avalon Stream specification in this document: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf
Basically you will just need to define your 8-bits as the data signal, and add a 'valid' signal that is asserted on each clock cycle that has a new valid data signal. If your interface doesn't support backpressure, just define a 'ready' input on your Avalon interface that you ignore. If on your incoming interface you have no 'valid' signal but have new valid data on each incoming clock cycle then you can just set valid to 1 on the Avalon side. And in that case I'd strongly suggest to run the SGDMA on a faster clock rate than your incoming signal, and put a dual clock FIFO between the DMA and your video input to cross the clock domain.
