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Altera_Forum
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21 years ago

Nios & Flash

Can the Nios cores handle the synchronous and/or burst modes of particular Flash devices in regards to instruction fetch?
Altera_Forum's avatar
Altera_Forum
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21 years ago

My apologies, this is in regards to the Nios II processor. I was reading up on the Avalon Bus Specification Reference Manual, and starting on page 83, it talks about Avalon tri-state slave read transfer with fixed latency for off-chip devices. Would this implementation accommodate our design? Since our software engineering team has decided to not have either instruction or data cache, we have elected to use the II/e core for now. From reading the other post, it seems like we can use the II/s core with the option of excluding the instruction cache in the Nios II 1.1 update.