Honored Contributor
Honored ContributorThe 'full template' code is larger and will be slower.
It is possible that you are just limited by the speed of the JTAG interface - so nothing you do on the fpga will help. To get nios code running as fast as possible you need to run with both code and data in tightly coupled memory areas. If you need to boot from JTAG (or flash) you'll need the instruction master interface and minimal instruction cache. If you code is slow, then make sure you are compiling everything with the optimiser enabled (-O3 is reasonable). It is also possibly to speed up code considerably by fine tuning the C source to avoid cycle stalls and mis-predicted branches (I got over 20% on the worst case path). You might even find you can do a better job of writing data to the JTAG uart than the Altera supplied drivers - particularly if you have very specific requirements.
