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Altera_Forum
Honored Contributor
Honored ContributorNewbie memory question
Hi, I got a Terasic DE0-nano board with a Cyclone IV FPGA. My design is writing data in the memory. I use a NIOS II softcore too and I'd like it to read the FPGA memory and the data I wrote in a h...
Altera_ForumHonored Contributor
Honored Contributorok, some points you may want to check:
* make sure your CPU reset vector (and exception vector) points to the right memory * your software will run, by default, in the biggest memory connected to your CPU. You can change that in the BSP Editor. * stdout must be correctly set to your jtag uart device in the BSP Editor * check for timing issues, it may cause your system to malfunction (or "no function" at all). Big on-chip memories will make it harder to route and may cause timing closure issues. * you may want to debug your software using Eclipse debug capabilities and run it step by step so you will know where and what it's going wrong (debug as -> niosII hw)
