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Altera_Forum's avatar
Altera_Forum
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12 years ago

Newbie memory question

Hi, I got a Terasic DE0-nano board with a Cyclone IV FPGA. My design is writing data in the memory. I use a NIOS II softcore too and I'd like it to read the FPGA memory and the data I wrote in a h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I've used another method:

In Qsys I've instantiated a dual-port memory. One is connected to the data_master for reading purpose, the other is exported and connected to the logic in the symbolic top-level for writing.

Tell me if that's bad.