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Altera_Forum
Honored Contributor
Honored ContributorNewbie memory question
Hi, I got a Terasic DE0-nano board with a Cyclone IV FPGA. My design is writing data in the memory. I use a NIOS II softcore too and I'd like it to read the FPGA memory and the data I wrote in a h...
Altera_ForumHonored Contributor
Honored ContributorBinome, these signals are connected automatically inside Qsys and are not necessarily meant to be exported.
That's why I've attached my own custom Avalon MM Bridge in my previous reply -- it doesn't have these additional symbols for different types of Avalon MM transactions (like variable latency and bus width adjustment). If you use my bridge it should be straightforward to connect the signals, otherwise you might like to read more about Avalon Interface -- http://www.altera.com/literature/manual/mnl_avalon_spec.pdf
