Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Newbie memory question

Hi, I got a Terasic DE0-nano board with a Cyclone IV FPGA. My design is writing data in the memory. I use a NIOS II softcore too and I'd like it to read the FPGA memory and the data I wrote in a h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

There's something I don't get:

I've read the documents and practiced some tutorials.

I've added an Avalon-MM pipeline bridge and connected it as you told me in my Qsys system. The symbol has ten new signals (waitrequest, readdata, readdatavalid, burstcount, writedata, address, write, read, byteenable, debugaccess) but my top-level on-chip memory has only 6 (clock, data, rdaddress, wradress, wren, q). How should I connect them?