Honored Contributor
Honored ContributorI'll let someone more familar with RTOSs answer 5-6
1) The .sof and .pof files are device programming files so they contain your actual hardware. Too me it sounds like your are confusing your software and hardware files 2) The .sof would have to be sent first (otherwise you have nothing to recieve the software components) 3) The .sof data is stored in the FPGA SRAM. So when the FPGA is powered down those contents are lost. If you want the contents to stay you must have some way to download these contents from some pre-populated non-volatile memory (Flash, EPCS are the two most likely types). So at powerup the non-volatile contents are restored back into the FPGA 4) If you do not have a license for Nios II or use any open core Altera IP, Quartus II compiles a sof that is time limited. This is meant to give you an evaluation copy of the IP so that you can try it out before purchasing it. When you download a time limited sof a window will open saying something like "leave the JTAG cable connected or this sof will time out". I hope that helps.
