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Honored Contributor
Honored ContributorNeed ideas on solving a weird LAN91C111 problem
I have a dual processor design with two /f cores. One processor, cpu_fifo, pulls data out of a fifo that is filled by a VHDL block receiving data from some proto pins. It copies the data into a share...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- originally posted by jakobjones@Jun 20 2006, 10:08 PM are you crossing clock domains? running one component at 50mhz and another at 100mhz? if so this is going to kill your performance because the sopc builder has to instantiate clock synchronization logic. it takes several clock cycles to pass data through the clock arbitrators.
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--- Quote End --- No I'm running everything off the same clock. There is a 33Mhz clock coming from off-board but that's only used in some VHDL blocks, SOPC builder and the Nios processor never see that signal.
