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Altera_Forum
Honored Contributor
Honored Contributorneed help on dma
I have a custom logic wrote by myself. There's a DCFIFO in the logic. And when the fifo is full, NIOS II cpu will get an interrupt, then cpu will get(read) data out of the fifo. Every thing seems all...
Altera_ForumHonored Contributor
Honored ContributorDon't use the falling edge, do everything on the rising edge.
You may want to configure your FIFO in showahead mode or add an extra read cycle on your Avalon interface. It could be a god idea to use a tool such as SignalTap to see what is happening on your Avalon slave interface.
