Honored Contributor
Honored ContributorI found wery clever solution to reduce your suggested 14 layer designe to 7-8 leyer design by making wery smart design.
Before I will tell my new teory of PCB making look at Sendero Evaluation kit bay microtroniX price 895$ in this Evaluation kit PCB layout they hade only one GND Layer and 2 VCC layers ather were signal layers and totaly they have 8 layer PCB. So Question is how can they make sutch designe? or they PCB is total garbage! I read in microtronix home page that they have cutting-edge hardware and software solutions then these sendero bord isn't total garbage and they use big EP2C35F672 device and how then about theyr firefly bords do they olso have 8 layer PCB. And here is my new PCB routing theory to reduce number of GND planes we can implement these GND fields in signal layer free spaces so 8 layer designe would lock like this: Top (signal layer 1 and GND) Signal 2 (gnd) Signal3 (GND) Signal 4 (GND) Signal 5 (GND Signal 6 (GND) VCC core (and few signals if there are left some not conected pins) VCC I/O (and few signals if there are left some not conected pins) ToTALY we have 6 GND Layers http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif witch is combined with signal layers but to do that we neede to make 4 lines in eatch signal layer to central GND pin block and this is done bay unrouting 3 pins in each side so totaly we will loose 12 pins per layer but as in the end we increase signal layer count bay 3 these lost pins we will route in theas layers. And I think that it is posible to make even 7 layer bord 5 GND and 2 VCC layers as you suggested, but only combined with Signal layers and finaly it wil be 2 times cheaper than making 14 layer bord! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif I think that this is the best solution!
