My multiprocessor test design.

hi,

I spent more than 1 month to implement a multiprocessor system. It is

made of two niosII cpu core and a modified uc/osII rtos is added to

surport it.

I'd like to share my experience here. This is the key point:

Hardware:

1.To identify each cpu,I implement a custom instruction to set and

read cpu id(it may support now),which are useful in operation system.

2.Since there is no atomic read-set instruction support in niosII.To

synchronize cpus,I implemented a user define spin-lock device.When cpus

read it,It return 1 to inform the cpu the it successfully locked,or

return 0 for failed. Then,cpus write the device to unlock.the device

contain 16 spin-locks,which are enough to OS to protect critical section.

It can aslo be used to atomicly read-set a memory location. So mutex

are easy to implement too.The total mount of mutexes used by

application(on us/os) are not limited.

3.Sending interrupt between cpus is needed to communicate between

cpus,for example, used by os to schedule tasks.To send interrupt between

cpus,I design a ipi(inter processor interrupt) device which has more than

one slave port, each port are connect to a single cpu with a same irq

number.Each cpu can access the device to send irq and associated data to

others.The irq and data are use to communicate between cpus.I used them

for task schedule only.

Software:

I modified the uc/os source code to support the smp architecture,

include the schedule part,context switch part and so on.To support niosII

with data cache, data cache flush are added in some part of the os core

to manage the cache coherence in software way.

Result:

I write a parallel application to test the system.

Both cpu work very FINE when data cache of the two cpu(niosII/s) are

not used.The speed is about two times than that of one cpu,if there is

not so many shared data.(it depends on the application) They run very

steady, and I believe more cpus are possible to add into it,although more

I/O collision will happen.

But,it sometimes crashed when cpu data cache (niosII/f) are used.

I have been seeking the error for a long time, but I have not found the

reason.I put alt_flush_dcache_all() every location where it may be

needed,but it still run error sometimes. I am now a little upset.

I design the system just for a homework, Since I am a newbie in fpga

field,I don't know how to evaluate the design. Is there some problems?

I'd like to know your comment.

btw: what does the arbitration priorty in sopc builder mean? why can't I

change them from 1 to 2?