My AXI4 Lite slave hangs CPU after read. Write transactions work correctly

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You may want to peruse this document: https://silica.avnet.com/wps/wcm/connect/e2612871-ffdd-470e-b355-f12e0f570395/silica_xilinx_designing_a_custom_axi_slave_rev1.pdf?mod=ajperes&cvid=liicqoz&cvid=liicqoz

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That's exactly, what I have used to design my bridge. See http://opencores.org/websvn,filedetails?repname=ax4lbr&path=%2fax4lbr%2ftrunk%2frtl%2faxil2ipb.vhd ;)

However this link is a "moving target"...

BTW. In this document there is nothing about avoiding combinational connections between input and output signals. That's why I have run into this incompatibility.

Thanks,

Wojtek

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That's exactly, what I have used to design my bridge. See http://opencores.org/websvn,filedetails?repname=ax4lbr&path=%2fax4lbr%2ftrunk%2frtl%2faxil2ipb.vhd ;)

However this link is a "moving target"...

BTW. In this document there is nothing about avoiding combinational connections between input and output signals. That's why I have run into this incompatibility.

Thanks,

Wojtek

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Can you show the combinatorial connections?

Now I already perused your code. Immediately I can't make much of it as it is rather complicated. I had expected to see a state-machine ... a state machine is worth a thousand equations

Regards,

Jos

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Can you show the combinatorial connections?

Now I already perused your code. Immediately I can't make much of it as it is rather complicated. I had expected to see a state-machine ... a state machine is worth a thousand equations

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Yes, the state machine is much clearer. However this design was based on an attempt to make the bridge as fast as possible.

Therefore the main part is a combinational process, which translates signals between the AXI4 Lite side and the IPbus (or WishBone in the second bridge) as fast as possible.

So the combinational connections are just results of the combinational process used here. An example may be, that in the write transaction:

If S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and there is no uncompleted transaction,

then if S_AXI_WSTRB = "1111", finally S_AXI_AWREADY and S_AXI_WREADY are set to '1'.

The above is done in a fully combinational way, creating the combinational connection between the input signals (AWVALID, WVALID, WSTRB ) and output signals (AWREADY, WREADY) at the AXI4-Lite side of the bridge.

Probably to comply to the requirement of avoiding combinational connections, I'll have to rewrite it as a state machine (hopefully for translated signals it will be the Mealy one).

However, almost for sure it will result in slightly slower (but safer) operation...

Regards,

Wojtek

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Yes, the state machine is much clearer. However this design was based on an attempt to make the bridge as fast as possible.

Therefore the main part is a combinational process, which translates signals between the AXI4 Lite side and the IPbus (or WishBone in the second bridge) as fast as possible.

So the combinational connections are just results of the combinational process used here. An example may be, that in the write transaction:

If S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and there is no uncompleted transaction,

then if S_AXI_WSTRB = "1111", finally S_AXI_AWREADY and S_AXI_WREADY are set to '1'.

The above is done in a fully combinational way, creating the combinational connection between the input signals (AWVALID, WVALID, WSTRB ) and output signals (AWREADY, WREADY) at the AXI4-Lite side of the bridge.

Probably to comply to the requirement of avoiding combinational connections, I'll have to rewrite it as a state machine (hopefully for translated signals it will be the Mealy one).

However, almost for sure it will result in slightly slower (but safer) operation...

Regards,

Wojtek

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Now your original code as hidden state! Where a State Machine proper will clearly indicate what your intentions are, in the case of a bunch of equations one has to decode all the equations and draw a timing diagram to understand what is going on. I even write State Machines with 2 (yes even only 2) states!

Now whether it is Mealy or Moore or a hybrid form doesn't really matter, that's for the academics. I divide my state machines in three parts:

1. a combinatorial part to decide on the next state, plus combinatorial outputs

2. a registered part with a reset to register the state, and to register possible output signals that require a known reset state

3. a registered part for the dataflow-type signals

I happened to work on an AXI4-Lite to Avalon MM bridge too :)

A state machine will make it easier to follow what the AXI4 master does, e.g. for a write transaction there a 3 transfers, address, write and response. These 3 may arrive in some sequence: A->W->R, A->WR, AW->R or even AWR.

Regards,

Josy