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Altera_Forum
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9 years ago

My AXI4 Lite slave hangs CPU after read. Write transactions work correctly

Hi, I have ported my AXI4-Lite to IPbus bridge from Zynq to Altera Cyclone V. Unfortunately, it behaves in a strange way in Cyclone V. Tests have been done with "devmem" tool in Buildroot comp...
Altera_Forum's avatar
Altera_Forum
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9 years ago

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You may want to peruse this document: https://silica.avnet.com/wps/wcm/connect/e2612871-ffdd-470e-b355-f12e0f570395/silica_xilinx_designing_a_custom_axi_slave_rev1.pdf?mod=ajperes&cvid=liicqoz&cvid=liicqoz

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That's exactly, what I have used to design my bridge. See http://opencores.org/websvn,filedetails?repname=ax4lbr&path=%2fax4lbr%2ftrunk%2frtl%2faxil2ipb.vhd ;)

However this link is a "moving target"...

BTW. In this document there is nothing about avoiding combinational connections between input and output signals. That's why I have run into this incompatibility.

Thanks,

Wojtek