Multiple SOPC Builder System

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originally posted by shmueld@Feb 6 2007, 12:35 PM

i currently have a working system that includes a nios ii cpu. i am trying to create a new design that that will have two such systems in a single chip (a stratix ii). i noted in the altera handbook for sopc that it was possible to instantiate multiple sopc builder systems as long as care is taken on the naming of the components. i have been able to generate two nios ii systems that are replica's of each other with changing the names of the systems and their components. the problems occurs when i try to complile. i have a seperate epcs controller in each nios ii system. when i compile i get the following errror

error: entity "epcs_controller_epcs_control_port_arbitrator" in file m4k1553pxiiicpusystem.vhd already exists in file m4k1553pxiiicpusystem_c2.vhd

i noticed that in the sopc that you can't change the name of the epcs controller nor does it allow you to intantiate more than one epcs controller. is there any way around this error ? does anyone know if it is possble in such a double system to have the epcs controller instantiated in both nios systems (for two seperate epcs chips)? i would prefer to try and design system in this manner in order to keep the system as close to the currently working design (as apposed to having a single epcs controller and a single larger epcs chip that could be used to configure both systems) . can anyone help me ?

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I&#39;m afraid I don&#39;t have good news for you on this one. The EPCS controller was designed that way on purpose. Note that when you add one to your system no pins pop out at the top level to connect it to the outside world. The reason is because Altera FPGAs that work with EPCS support configuring from them; there is one set of dedicated pins that the FPGA can use at power-up to configure from (before Nios is even alive). The EPCS controller core in SOPC Builder expects to use these dedicated pins, and as such the verilog code the EPCS controller generates "asks" Quartus to use these special EPCS pins.

What this means is that there is a limitation of exactly one EPCS controller peripheral *per chip*, at least the way the product is setup today.

Of course, we are talking programmable logic. You could wire up as many EPCS chips as you wanted to general purpose IO, with the only restriction being that only one of them could confiure the FPGA per my statement above. To support this, though, would require that our EPCS controller IP had a mode to export its pins to the top, which it doesn&#39;t currently have...