Multiple processors fail to communicate with peripherals
I have a working single-processor build on a cyclone III, running at 100 MHz that includes a jtag-uart, and RS-232 UART, some debug output PIO pins, etc. Everything in the SOPC system is running at 100 MHz. I am wanting to divide my project into two NIOS processors. I added a 2nd NIOS along with a timer, some dual-port on-chip memory, and a mutex, similar to the multiprocessor design tutorial. Both processors run from SDRAM (different offset addresses). I am trying to get this up and running, using slightly modified hello_world_multi.c file to test it. However, when I try to run the multi-processor build, I don't see any prints on the NIOS II terminal. I tried using the RS-232 UART for the print statements and also tried toggling the debug pins, and none of it seems to work. I can step through the code in debug mode just fine, and it seems to work as expected, except that when it executes the printf() command, nothing happens.
I have tried variations of the SOPC system, adding and removing pipeline bridges. The result is usually the same, although sometimes one of the processors will fail verify or will simply be left paused. I am wondering if putting in the second processor and related peripherals has somehow screwed up the timing in the SOPC system? I wonder if I need to change the phase shift on the PLL for the SDRAM clock? That doesn't seem to make sense since (at least on a couple of my builds) I seem to be able to operate from the SDRAM just fine, but cannot seem to communicate to the other peripherals. Is the fact that my peripherals are behind a pipeline bridge an issue? I would think that would help the performance.