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Altera_Forum's avatar
Altera_Forum
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19 years ago

Multiple PLLs

Setup:

I'm trying to create system that contains the audio core provided in the University IP cores. I have configured it properly and included both the DE board external interface and audio and video configuration. I also included the SDRAM from this collection as well. I set up the pins in a block diagram and connected them with the proper pin assignments.

Problem:

When compiling the application in Quartus 6.0 I get an error describing that my "CLOCK_50 cannot feed more than one PLL." Now I know my PLL are being generated by the DE board external interface component I included in the SOPC. One is generated for the Audio component and the other for the SDRAM. What I dont know is what is exactly causing this error and how to resolve it. If anyone has more knowledge on this topic or could help me specifically with this design please let me know. Also if anyone has used these cores together successfully that would be helpful too.

Thanks in advance

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    The error means exactly what it says. Your CLOCK_50 is obviously the top level clock input pin. You must be using it as an input to more than one PLL in your design. On your top level, do a search for CLOCK_50 and see what it's feeding. Also, you may be doing it inside your SOPC system.

    One thing you might try (and I really have no idea if this will work) is to set the AUTO_MERGE_PLLS logic option for the project. I don't know what stage your compile failed at. If it was during the Fitter stage, the fitter may be smart enough to merge your PLLs together. The real solution is to fix your design.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    You may manually combine all the clock generation into a single PLL.

    IzI