Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorMultiple PLLs
Setup: I'm trying to create system that contains the audio core provided in the University IP cores. I have configured it properly and included both the DE board external interface and audi...
Altera_ForumHonored Contributor
Honored ContributorThe error means exactly what it says. Your CLOCK_50 is obviously the top level clock input pin. You must be using it as an input to more than one PLL in your design. On your top level, do a search for CLOCK_50 and see what it's feeding. Also, you may be doing it inside your SOPC system.
One thing you might try (and I really have no idea if this will work) is to set the AUTO_MERGE_PLLS logic option for the project. I don't know what stage your compile failed at. If it was during the Fitter stage, the fitter may be smart enough to merge your PLLs together. The real solution is to fix your design.
