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19 years ago

Multiple PLL clock error

Anyone that has any insight to this please help! Thanks! My set-up is I am trying to make a project using the VGA of my DE1 Altera Development board as well as the SDRAM. In SOPC Builder:...
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Altera_Forum
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19 years ago

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originally posted by zippyua@Mar 1 2007, 05:04 PM

anyone that has any insight to this please help! thanks!

my set-up is i am trying to make a project using the vga of my de1 altera development board as well as the sdram.

in sopc builder:

i am using the deboards external interface and i have the boxes selected to create a clock signal for sdram as well as vga.

i am using altera's university program vga ip.

my clock signals are as follows:

clk - external - 50 mhz

dram_int_clk - external - 50 mhz

vga_int_clk - vga<-de_board - 25 mhz

note: i tried the design two ways the latest is as stated above. the other is i tried it without the "dram_int_clk" clock at all thinking maybe the external interface would just take care of it all. my choices for clock source for the dram_int_clk are &#39;external&#39; &#39;vga<-de_board&#39; and a blank choice. it would make perfect sense and really seems like there should be a &#39;dram<-de_board&#39; option since it seems like thats created by the external interface. but this option does not exist.

current quartus set-up:

in the block diagram i have the clock output signal created by the system for the dram wired back around to the &#39;dram_int_clk&#39; input pin to the block diagram. there is the boards 50mhz clock pin assigned to the input pin to the clk signal input. there is an output for the vga_int_clk signal but i am currently not doing anything with that signal.

when i compile:

sythesis completes

fitter fails and i get the message "input clock "clk" cannot feed more than one pll"

i am confused most by this because i am not directly assigning the clock signal &#39;clk&#39; to anymore than one pin. i&#39;ve read that you can manually combine clock generation signals into one pll but i have no idea how to go about doing that. and if i do do it will the clock signals maintain their present phase shifts?

again, any insight from anybody will be greatly appreciated! thanks everyone!

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