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Altera_Forum
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19 years ago

Multiple PLL clock error

Anyone that has any insight to this please help! Thanks!

My set-up is I am trying to make a project using the VGA of my DE1 Altera Development board as well as the SDRAM.

In SOPC Builder:

I am using the DEBoards external interface and I have the boxes selected to create a clock signal for SDRAM as well as VGA.

I am using Altera's University Program VGA IP.

My clock signals are as follows:

clk - External - 50 Mhz

dram_int_clk - External - 50 Mhz

vga_int_clk - VGA<-DE_board - 25 Mhz

Note: I tried the design two ways the latest is as stated above. The other is I tried it without the "dram_int_clk" clock at all thinking maybe the external interface would just take care of it all. My choices for clock source for the dram_int_clk are &#39;External&#39; &#39;VGA<-DE_Board&#39; and a blank choice. It would make perfect sense and really seems like there should be a &#39;Dram<-DE_Board&#39; option since it seems like thats created by the external interface. But this option does not exist.

Current Quartus Set-up:

In the block diagram I have the clock output signal created by the system for the DRAM wired back around to the &#39;dram_int_clk&#39; input pin to the block diagram. There is the boards 50Mhz clock pin assigned to the input pin to the clk signal input. There is an output for the vga_int_clk signal but I am currently not doing anything with that signal.

When I compile:

Sythesis completes

Fitter fails and I get the message "Input clock "clk" cannot feed more than one PLL"

I am confused most by this because I am not directly assigning the clock signal &#39;clk&#39; to anymore than one pin. I&#39;ve read that you can manually combine clock generation signals into one PLL but I have no idea how to go about doing that. And if I do do it will the clock signals maintain their present phase shifts?

Again, ANY insight from anybody will be GREATLY appreciated! Thanks everyone!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    --- Quote Start ---

    originally posted by zippyua@Mar 1 2007, 06:04 PM

    anyone that has any insight to this please help! thanks!

    my set-up is i am trying to make a project using the vga of my de1 altera development board as well as the sdram.

    in sopc builder:

    i am using the deboards external interface and i have the boxes selected to create a clock signal for sdram as well as vga.

    i am using altera&#39;s university program vga ip.

    my clock signals are as follows:

    clk - external - 50 mhz

    dram_int_clk - external - 50 mhz

    vga_int_clk - vga<-de_board - 25 mhz

    note: i tried the design two ways the latest is as stated above. the other is i tried it without the "dram_int_clk" clock at all thinking maybe the external interface would just take care of it all. my choices for clock source for the dram_int_clk are &#39;external&#39; &#39;vga<-de_board&#39; and a blank choice. it would make perfect sense and really seems like there should be a &#39;dram<-de_board&#39; option since it seems like thats created by the external interface. but this option does not exist.

    current quartus set-up:

    in the block diagram i have the clock output signal created by the system for the dram wired back around to the &#39;dram_int_clk&#39; input pin to the block diagram. there is the boards 50mhz clock pin assigned to the input pin to the clk signal input. there is an output for the vga_int_clk signal but i am currently not doing anything with that signal.

    when i compile:

    sythesis completes

    fitter fails and i get the message "input clock "clk" cannot feed more than one pll"

    i am confused most by this because i am not directly assigning the clock signal &#39;clk&#39; to anymore than one pin. i&#39;ve read that you can manually combine clock generation signals into one pll but i have no idea how to go about doing that. and if i do do it will the clock signals maintain their present phase shifts?

    again, any insight from anybody will be greatly appreciated! thanks everyone!

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=21948)

    --- quote end ---

    --- Quote End ---

    First off, I don&#39;t know if the VGA is supported in the University IP core at this point. You can generate your own clock though. I recommend not using the DE2 external interface component despite what they say. I did a similar project with the University audio core. I created a pll block diagram that took its input from the clock 50 and had to outputs with the proper clock division. I don&#39;t know what that would be for the VGA portion but if you sift through the code I&#39;m sure you&#39;ll find it. Don&#39;t forget if you are using SDRAM which I&#39;m not sure if you are that you generate a time offset within the PLL diagram.

    Best of Luck
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    --- Quote Start ---

    originally posted by zippyua@Mar 1 2007, 05:04 PM

    anyone that has any insight to this please help! thanks!

    my set-up is i am trying to make a project using the vga of my de1 altera development board as well as the sdram.

    in sopc builder:

    i am using the deboards external interface and i have the boxes selected to create a clock signal for sdram as well as vga.

    i am using altera&#39;s university program vga ip.

    my clock signals are as follows:

    clk - external - 50 mhz

    dram_int_clk - external - 50 mhz

    vga_int_clk - vga<-de_board - 25 mhz

    note: i tried the design two ways the latest is as stated above. the other is i tried it without the "dram_int_clk" clock at all thinking maybe the external interface would just take care of it all. my choices for clock source for the dram_int_clk are &#39;external&#39; &#39;vga<-de_board&#39; and a blank choice. it would make perfect sense and really seems like there should be a &#39;dram<-de_board&#39; option since it seems like thats created by the external interface. but this option does not exist.

    current quartus set-up:

    in the block diagram i have the clock output signal created by the system for the dram wired back around to the &#39;dram_int_clk&#39; input pin to the block diagram. there is the boards 50mhz clock pin assigned to the input pin to the clk signal input. there is an output for the vga_int_clk signal but i am currently not doing anything with that signal.

    when i compile:

    sythesis completes

    fitter fails and i get the message "input clock "clk" cannot feed more than one pll"

    i am confused most by this because i am not directly assigning the clock signal &#39;clk&#39; to anymore than one pin. i&#39;ve read that you can manually combine clock generation signals into one pll but i have no idea how to go about doing that. and if i do do it will the clock signals maintain their present phase shifts?

    again, any insight from anybody will be greatly appreciated! thanks everyone!

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=21948)

    --- quote end ---

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    --- Quote Start ---

    originally posted by zippyua@Mar 1 2007, 05:04 PM

    anyone that has any insight to this please help! thanks!

    my set-up is i am trying to make a project using the vga of my de1 altera development board as well as the sdram.

    in sopc builder:

    i am using the deboards external interface and i have the boxes selected to create a clock signal for sdram as well as vga.

    i am using altera&#39;s university program vga ip.

    my clock signals are as follows:

    clk - external - 50 mhz

    dram_int_clk - external - 50 mhz

    vga_int_clk - vga<-de_board - 25 mhz

    note: i tried the design two ways the latest is as stated above. the other is i tried it without the "dram_int_clk" clock at all thinking maybe the external interface would just take care of it all. my choices for clock source for the dram_int_clk are &#39;external&#39; &#39;vga<-de_board&#39; and a blank choice. it would make perfect sense and really seems like there should be a &#39;dram<-de_board&#39; option since it seems like thats created by the external interface. but this option does not exist.

    current quartus set-up:

    in the block diagram i have the clock output signal created by the system for the dram wired back around to the &#39;dram_int_clk&#39; input pin to the block diagram. there is the boards 50mhz clock pin assigned to the input pin to the clk signal input. there is an output for the vga_int_clk signal but i am currently not doing anything with that signal.

    when i compile:

    sythesis completes

    fitter fails and i get the message "input clock "clk" cannot feed more than one pll"

    i am confused most by this because i am not directly assigning the clock signal &#39;clk&#39; to anymore than one pin. i&#39;ve read that you can manually combine clock generation signals into one pll but i have no idea how to go about doing that. and if i do do it will the clock signals maintain their present phase shifts?

    again, any insight from anybody will be greatly appreciated! thanks everyone!

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=21948)

    --- quote end ---

    --- Quote End ---

    The problem seems to be the University Program VGA IP core. Very poorly put together and rushed to release. The VGA core itself works, but don&#39;t use recommended secondary core for the clocks. Just add your own PLL instead and configure using the specs in the .pdf for the VGA core.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I have the same error caused by multiple PLL clock error.

    I am using de2 which only has ONE CLOCK_50. However, i need to drive 2 PLL. What should i do?..

    I am the beginner and hope experts can give me some advices. Thanks a lot.