Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Multiple NiosII System

Hello everybody!

It's my first post on this forum so a quick presentation to start :

I'm a french student in the engineering school Polytech'Paris UPMC and I'm actually working on FPGA for a telepresence robot project.

The robot we are working on is a telepresence robot which will be controled by internet. This robot must enable the user to interact with the robot environment using bidirectional sound and video transmission between the robot and a computer. The robot is connected to the Internet using an Ethernet connection to a Wifi-Ethernet bridge.

I'm working on a NiosII system running uCLinux and we are very satisfied by this solution which works perfectly for the moment. The problem is that we need a more powerful system to achieve some video compression for example, and a single NiosII processor running uCLinux will not be able to provide us the computation power we need for that.

That's why I am thinking to the possibility of using a multi core system. My idea is to use only one NiosII running uCLinux, and an other to run a C program compiled with the Nios IDE just to perform some video compression and to stock the data in a shared memory between the two processor.

I think that it is possible, and because we are working on DE2-70 board, we have enough memory to do it. It is possible to associate each processor with a JTAG UART Ip and to program them separately, but we will not be able to use this solution because we need the board to boot in autonomy.

So after this long (long) introduction, here is my question.

Is it possible, and if yes how can we do it, to use the flash memory of the board in order to program the RAM of each NiosII which will run two different and independent programs ?

I think that it is impossible to share a CFI flash between the two NiosII due to read/write conflict.

I've red that it could be possible to make one CPU programming the RAM of the second but I don't know how to do that?

Thank you very much

Nicolas

15 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    That sounds silly, one of the cpus had set everything for the second, then release it from soft reset.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    hi......

    you can put one cpu to write ...... and 2 cpus reads.......

    if cpu 2 want to write send data to onchip for example and send a flag for another cpu write to flash ......

    at the starts one of then need to start first ........ the two cpus only can start at same time if you had more than one flash......

    you can put a cpu_reset_request pin at cpu at sopc_builder and conect at a pio in another cpu......... one cpu starts normaly and the other start at reset..... after the first cpu starts you can set the pio and start second cpu using the same flash.....

    you can put two system at sopc buider and put a onchip memory with two cpus conect share data bus.......to communicate the two cpus.... no problem with share data bus because you put this onchip working with lower clock (tip) than cpus.......

    cheers

    Franz Wagner
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    What about making your compression some hardware blocks a la c-to-hardware compiler? There are other options especially around the internet that will do this type of compilation for you for free, but I can't speak to their actual performance. IF you can port your algorithm to hardware it will certainly be faster than a software implementation.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    What about making your compression some hardware blocks a la c-to-hardware compiler? There are other options especially around the internet that will do this type of compilation for you for free, but I can't speak to their actual performance. IF you can port your algorithm to hardware it will certainly be faster than a software implementation.

    --- Quote End ---

    can u explain ????? i cant underestand..... sorry......