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Altera_Forum
Honored Contributor
Honored ContributorMultiple NiosII System
Hello everybody! It's my first post on this forum so a quick presentation to start : I'm a french student in the engineering school Polytech'Paris UPMC and I'm actually working on FPGA for a ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- What about making your compression some hardware blocks a la c-to-hardware compiler? There are other options especially around the internet that will do this type of compilation for you for free, but I can't speak to their actual performance. IF you can port your algorithm to hardware it will certainly be faster than a software implementation. --- Quote End --- can u explain ????? i cant underestand..... sorry......
