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Altera_Forum
Honored Contributor
15 years agomulticycle instruction FSM with nios and the done variable
I have been trying for weeks to figure out how the done variable works and it seems like it has no effect whatsoever on the program. Can anyone explain how it works. Here's an example i've bee...
Altera_Forum
Honored Contributor
15 years agoHello, thanks for helping
If i put start=1 just for one clock cycle, there is no result given in the simulation. If I put start for both of the 2 sets of inputs (so 2 cycles), i get the results i expect as shown in the image below (Fig 1). Maybe I don't have the SOPC set up correctly. -I have a NIOS2/e core to which i added the custom instruction as a CI slave and didn't change any of the settings there. Maybe there needs to be a variable in "Clock Cycles" when i add the CI as shown in Fig2. -on chip memory -sysid -jtag uart As i said, the CI works from NIOS in the c program, but the result is delayed by a call, so i have to call (1,x,y) twice to get the result. http://skiareatrailmaps.com/images/simulation2.JPG http://skiareatrailmaps.com/images/compoment_editor.JPG Also, tried changing the code to this, but no change. Don't know if I understood what you meant. if (reset = '1') then
state <= s0;
ELSIF (clk'EVENT AND clk = '1') THEN
CASE state IS
WHEN s0 =>
IF (start = '1' AND n = '0') THEN
io_148194546 <= dataa;
io_277277265 <= datab;
state <= s0;
done <= '1';
ELSIF (start = '1' AND n = '1') THEN
io_109970892 <= dataa;
io_19111827 <= datab;
state <= s1;
done <= '0';
ELSE
state <= s0;
done <= '1';
END IF;
WHEN s1 =>
result <= io_1298736395;
done <= '1';
state <= s0;
WHEN OTHERS =>
report "Invalid State";
END CASE;
END IF;
END PROCESS; Thanks again!