multicycle instruction FSM with nios and the done variable

oops, i posted the wrong version of the FSM code. the only diff is that i have done <= '0' in the n=1 case in state s0. The simulation also works as I expect it to, an image of it is included at the bottom. But if I run the code on a nios II core on the DE0 board, it doesn't work. The results are delayed as described above with the same code.

PROCESS (reset, clk)
BEGIN
if (reset = '1') then
state <= s0;
    ELSIF (clk'EVENT AND clk = '1') THEN
        CASE state IS
            WHEN s0 =>
                IF (start = '1' AND  n = '0') THEN
                    io_148194546 <= dataa;
                    io_277277265 <= datab;
                    state <= s0;
                    done <= '1';
                ELSIF (start = '1' AND  n = '1') THEN
                    io_109970892 <= dataa;
                    io_19111827 <= datab;
                    state <= s1;
                    done <= '0';
                ELSE
                    state <= s0;
                    done <= '1';
                END IF;
            WHEN s1 =>
                result <= io_1298736395;
                done <= '1';
                state <= s0;
            WHEN OTHERS =>
                report "Invalid State";
        END CASE;
    END IF;
END PROCESS;
END behavior;