Multicycle Custom Instructions

Hi,

I want to implement a multi-cycle custom instruction and I have written a Verilog code for the same. However, I am not able to find any information on how I should assert the various input signals (eg. start, clk_en, etc) from the Nios IDE. i.e I want to know how I should do this from the main function. I would appreciate if someone could tell me the syntax for asserting input signals to the custom instruction.

Any help extended would be highly appreciated.

Thanks

Sai