mSGDMA transfer from DDR3 using FPGA2HPS-SDRAM interface

Hi,

I am using a DE1-SoC board equipped with Cyclone V SoC, I have a custom circuit on FPGA with Avalon interface, I want to transfer some data from the DDR3 (of the HPS) to this circuit. I used an mSGDMA to do that. I am using linux and I began with a false driver so I control all of this from the user space using mmap() function.

In Qsys I activated the the F2S interfaces, I connected the read port of the mSGDMA to this interface (avalon than AXI), and the write port to my circuit. both of the ports are 32 bits data wide.

I have mmaped a region on SDRAM to write directly to it the source data, I mmaped the csr and descriptor reg too. the preloader and all headers file are updated according to the design.

The Linux stuck when the transfer begin.

I have used SignalTapII to find the problem.

first observation is the transfer begin, it transfers the eight beats of addresses then it reads one beat of data and it stuck.

second when I am using avalon on the F2S interface:

the address demanded by the mSGDMA (which is the same as my c program) is divided by 8 in the input of the F2S interface, which is not the problem when I choose an AXI interface.

I would like to know where is the problem, is there any one who face this problem yet.

If It is possible, is there any tutorial that shows the procedure to read data from F2S interface

Thanks