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Altera_Forum
Honored Contributor
12 years agomSGDMA and interrupt issue
Hi, I've tried to port the example from the mSGDMA wiki page to the DE2-115 board. Instead of the DDR-Controller I use the SDRAM controller. Now I've got the following strange issue. (1)...
Altera_Forum
Honored Contributor
12 years agoI was able to resolve my issue by myself:
So for anyone who may encounter this thread in the future: The interrupt signal triggered, but the NIOS processor did not call the interrupt service routine. Unfortunately the interrupt seems to remain signalled even the system reset is pulled down. I've read somewhere that the IRQ is intentionally latched, but I'm not so sure if this should also persist after resets. The main problem was then actually that I already placed the isr in a tightly coupled memory (should have mentioned that in the original post), this prevented the isr from actually getting called. I assume I'm missing something in the Qsys wiring, since the manuals state that putting isr's in a tightly coupled memory region is a recommended procedure to reduce isr latency. I'm still grateful if somebody takes the time to give me some short explanations for the phenomenas I've seen. I'm quite busy getting my intended design up and running, so I'm unable to dig deeper why it didn't play out originally.