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Altera_Forum's avatar
Altera_Forum
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20 years ago

MRAM for cache with multi-NIOSII build

I'm trying to project the maximum number of NIOS processors that I can put in various Stratix / Stratix II FPGAs for various instruction and data cache sizes. I'm assuming that the best wa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

In the current Nios II 1.1 release, the data cache cannot use M-RAMs due to differences between M-RAMs and M4Ks.

However, I've redesigned the data cache for the next Nios II release due in May so that it can use M-RAMs.