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Altera_Forum
Honored Contributor
13 years agomissing vertical sync signal on clocked video output Core
The video IP core I am working on is working. But there is one problem, the output vertical sync signal is missing from clocked video output Core. Please help me to find what is the rea...
Altera_Forum
Honored Contributor
13 years agoIn the Qsys component editor, there is an option for the sync signals. "Embedded in video" or "On separate wires". You need to select "On separate wires".
See page 11-4 of ug_vip.pdf