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Honored Contributor
Honored ContributorMetaStability
How long is the duration of metastability in a flipflop? If metastability occurs in one cycle i.e. data edge coincides with clock edge and in the next cycle data is stable at the clock edge, will the...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The data signal is generated at 122.88 MHz and sampled at 153.76 MHz via two synchronizers. Is it required to pulse stretch the data signal? The sampling clock is faster than the data signal. --- Quote End --- I think your problem is not metastability per se but how to pass data fom one clock domain to other. If you want to keep sampling rate as 122.88 then use dc fifo if you want to upsample to new rate then use filter
