Memory verification issue

Thanks for the help,got this thing resolved,by a fluke.Here is how i got to the fluke:i have tried to run the example design of arria II development board,6g edition.By the way,you ALWAYS get constraint warnings,at least on development board examples,even if you don't change the example by any way).It worked.Then i have looked carefully at sopc connections of the design example (bts_config).I have noticed that descriptor outputs of both sg-dma are connected to descriptor memory,but the memory i/o are connected both to onchip-ram memory and to ssram memory (through tri-state bridge).In my SG-DMA example based design i have instansciated an on chip ram and did the same,and it worked!Then i removed the onchip ram set the reset vector and exception vectors to external ssram and it still worked!Haleluya.... :)