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Altera_Forum
Honored Contributor
Honored ContributorMemory access from Nios I
Hej ! I'm quite a newbie to Nios 1 so it may be quite easy but I don't figure out how to do this : I have a peripheral which I declared as a user-logic component in SOPC Builder and as a m...
Altera_ForumHonored Contributor
Honored ContributorHello Fly,
Yes, all your CS and R/W should be ok. The behaviour of your own logic and how you have setup the PIO will determine the code you need to clear the interrupt. I'm presuming that your logic has a register, or something, that you must write in order to clear its interrupt line, you can then clear the PIO interrupt by writing zero to the edgecapture bit. Is it possible the PIO is setup for level and you aren't clearing the interrupt in your own logic yet? This would cause continuous interrupts. Banx.
