MCP2515 CANbus implementation in NIOS using alt_avalon_spi_command on 10M50DA

Hi, I have started to work on MCP25625, which is similar to your MCP2515. Were you able to get it to work for you with nios?

Hi Nitin123,

Based on your comment, it should be safe to assume that:

• the Nios II is online & working
• the SPI HAL driver is present & can access the SPI Core soft IP
• the IO is working fine (Observed SPI transaction on the bus line)

With that, I would suggest comparing the observed SPI transaction with the MCP2515 sample waveforms.

And check if there are any differences.

https://ww1.microchip.com/downloads/en/DeviceDoc/MCP2515-Stand-Alone-CAN-Controller-with-SPI-20001801J.pdf

For example,

With this Read Instruction, failure may be caused by:

• nCS line is not at logic ‘0’ level throughout the whole SPI transaction.
  (Especially when there are multiple SPI agents, and the SPI Core soft IP might select the wrong nCS line)
• Instruction sent in SI line is invalid.
• Address Bytes sent in SI line is invalid.
• SCK clock cycles ends prematurely.

Besides that, please review the following SPI Core settings in your design.

• SPI Clock (sclk) Rate
  

• Specify Delay
  
  
  
  
• Timing Settings

Altera’s SPI Core supports all SPI Modes.
The MCP2515 supports Mode 0,0 & Mode 1,1 only.

Regards,

Hello Sir,

Thank you for your prompt response.

This is the timing diagram from my logic analyzer, which confirms that the chip select (CS) line remains low throughout the entire SPI transaction. Each command, address, and data byte is transmitted in 8-bit segments. There's an observed delay of approximately 11.8 µs between bytes, which, according to various sources, is within normal expectations. The SPI clock operates continuously during each 8-bit transfer, and the CS line stays low for the full duration of the transaction, encompassing command, address, and data phases.​

In my Qsys design, the SPI clock was initially set to 10 MHz but now it is 1 MHz : MCP2515's maximum supported frequency is 10 MHz. Additionally, SPI mode 0,0 has been selected, as supported by the MCP2515.​

I have two specific concerns:

1. Chip Select Behavior: Initially, I used the macro:
IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(SPI_BASE, SPI_SLAVE_SEL);

However, this caused the chip select line to toggle every 8 bits. To address this, I switched to using the alt_avalon_spi_command function, which maintains the chip select line low throughout the entire transaction, ensuring proper communication with the MCP2515.

2. Utilizing HPS CAN Controller Without DDR: Our custom Cyclone V SoC board lacks DDR memory, preventing the use of a full-fledged embedded Linux system. I'm considering leveraging the HPS-side CAN controller by writing a bare-metal program that operates from the internal SRAM (approximately 64 KB). Is this approach feasible given the memory constraints? If so, could you provide any sample programs or guidance on implementing this?

Now for mcp2515, I believe the software setup is correct, but to rule out hardware issues, I've ordered additional MCP2515. Any insights or sample code you can share would be immensely helpful.

Thank you

I am not able to see your example code in the attached zip file. These are the basics steps you may start your debugging. It could be the hardware setup, the fpga configuration or the software code you have.

To interface an Altera FPGA (such as the 10M50DA from the MAX 10 series) with an MCP2515 CAN controller using the Avalon SPI interface, you will need to follow a series of steps involving both hardware and software configurations. Here's a general guideline to get you started:

Hardware Setup

1. Connect the MCP2515 CAN Controller to the FPGA:

   • Use SPI connections (MOSI, MISO, SCK, CS) between the FPGA and the MCP2515.
   • Ensure the CAN transceiver is connected to the MCP2515 for signal conditioning and protocol compliance.

2. Provide Power and Ground Connections:

   • Make sure both devices are powered and grounded appropriately according to their respective datasheets.

3. Crystal Oscillator for MCP2515:

   • The MCP2515 typically requires a crystal oscillator for timing; make sure it's connected and configured correctly.

FPGA Configuration

1. Design SPI Master in FPGA:

   • Use the Quartus Prime software to design an SPI master module using the Avalon MM interface.
   • Instantiate the SPI master and connect it to your design. Ensure it includes proper clocking and data rate configurations compatible with the MCP2515.

2. Pin Assignment:

   • Assign the pins in your FPGA design correctly to match your physical connections.

Software Implementation

1. Using alt_avalon_spi Commands:

   • The Altera alt_avalon_spi API provides a way to handle SPI communications. Ensure you have included this API in your project.

2. Initialize SPI Interface:

   • Initialize the SPI interface using the appropriate commands, such as setting up baud rates, SPI mode (likely Mode 0 for MCP2515), and chip select configurations.

3. MCP2515 Configuration:

   • Write software routines to configure the MCP2515 registers. This includes setting up CAN bit timing (refer to the MCP2515 datasheet).
   • Enable necessary MCP2515 features, such as enabling interrupts if desired.

4. Basic Commands:

   • Use alt_avalon_spi_command() to send and receive data to/from the MCP2515. You'll typically start with setting control registers and then move onto read/write operations for CAN messages.