Honored Contributor
Honored ContributorThanks for your reply.
Of course I need to implement more than a processor and a mac+phy. I have a specialized logic glue to implement and the FPGA is needed. The question for me is to chose one of those: 1 - ATOM + Chipset + Ethernet chip + PCI Bridge + FPGA. In this case the FPGA include only specific logic (with an FPGA like EP1C3) 2 - ATOM + Chipset + FPGA + PHY. In this case the FPGA include specific logic + PCI Bridge + Ethernet. 3 - Only FPGA + PHY. I already use the solution 1, so I now it works. But it takes a lot of place on my PCB, componants aren't very expensive, but they are a lot and the production cost is high. The solution 2 is software difficult and need a FPGA with transceiver. The solution 3 would be the best if: - the fpga componant is not so expensive (less than $150) - network perfomance is enouth: my maximum transfert rate is 4.9MBytes/s with TCP. As ykozlov find a maximum rate of 30Mbit/s with TCP (so 3.75MBytes/s), I'm thinking that we are near the objective. What would be the impact of JUMBO frame one the data rate. If the nios processor take time to read and create ethernet/tcp header, it should change the data rate? Does somebody try it?
