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Altera_Forum
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15 years ago

Max throughput of SOPC DMA?

Hello, Currently I have a system with DMA transfers and DDR2 SDRAM (and a lot of other stuff). I'm using the normal SOPC builder DMA controller. I run the system on 100 MHz, the DDR2 SDRAM run...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

What are the source and destination memories? What are the source and destination data widths? And what are the max burst count setup for those memories and the SGDMA?

The design example shows very limited performance because of the following:

a) The source and destination memory are the same (i.e. throughput cut in half)

b) The arbiter is letting the read and write masters access the memory with burst of 2 transactions back and forth which will thrash SDRAM (SDRAM performs best with a bunch of back to back sequential accesses).

So really the way the design example is setup for SDRAM it's giving probably the worst case performance possible.