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Altera_Forum's avatar
Altera_Forum
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19 years ago

max 32-bit onchip_memory in EP2C8?

I am creating a simple NIOS II system that runs entirely off of onchip_memory RAM. According to the datasheet, the Cyclone II EP2C8 has approximately 20 kB of internal memory. I am using the simplest Nios II/e core (no caches) and the following components:

cpu

onchip_memory

jtag_uart

sysid

pio

epcs_controller

uart

The problem is that I can't generate a very large block of 32-bit onchip_memory without getting an "Error: Can't place 128 RAM cells or portions of RAM cells in design" during compilation in Quartus II. The largest block that I have been able to create is 8 kB! I can make an 8 kB RAM, 4 kB ROM, and 2 kB instruction cache successfully, but nothing more than a single 8 kB RAM by itself.

Do I have any other options for expanding my available internal memory for storing / running my program? I'd like to use as much of the 20 kB as possible. Adding external memory is not an option unfortunately. Thanks for any help.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    So apparently the issue is related to how Quartus is configuring the M4K blocks. For a 12 kB block of 32-bit wide memory, Quartus chooses to run the M4K in 4096x1bit mode because 4096 > ((12*1024)/(32/8)) > 2048. This then uses 32 M4K blocks and wastes a good amount of each.

    Apparently you can modify the onchip_memory_0.v file after its generated by SOPC builder to try and force an M4K configuration. In the case of 12 kB, if 128x32bit is used, then only 24 M4K blocks are needed. Adding the line "// the_altsyncram.maximum_depth = 128" to line 94 in the onchip_memory_0.v file forced this configuration and allowed successful fitting of a 12 kB memory block. This was the largest block I was able to configure while still maintaining a 2 kB instruction cache in the NIOS II/s. Using a NIOS II/e (no instruction cache) instead, I'm able to generate up to a 14 kB block successfully.