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DR123's avatar
DR123
Icon for New Contributor rankNew Contributor
6 years ago

MAX 10 EMIF DDR3 low transfer rate

Hi, I’m working with a MAX 10 device (DECA development board) to transfer data from a FIFO to the DDR3. I’m using a Scatter Gather DMA and a EMIF DDR3 controller to transfer the data. The DMA works ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

To isolate your issue to find the bottleneck, you can start with small design first then only slowly add more design block into it.

For instance :

  1. Create DDR3 only design and test the performance
  2. Then upgrade to DDR3 + DMA design (without using QSYS)
  3. Then upgrade to DDR3 + DMA design (with using QSYS)

Thanks.

Regards,

dlim